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W9412G6JH
CLK
V X
V X
V X
V ICK
V X
V ICK
V X
V ID(AC)
CLK
V SS
V ID(AC)
0 V Differential
V ISO
V ICK
V ICK
V ISO(min)
V ISO(max)
V SS
(16) t AC and t DQSCK depend on the clock jitter. These timing are measured at stable clock.
(17) A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
(18) t DAL = (t WR /t CK ) + (t RP /t CK )
For each of the terms above, if not already an integer, round to the next highest integer.
Example: For -5 speed grade at CL=2.5 and tCK=6 nS
t DAL = ((15 nS / 6 nS) + (15 nS / 6 nS)) clocks = ((3) + (3)) clocks = 6 clocks
(19) For command/address input slew rate ≥1.0 V/n S.
(20) For command/address input slew rate ≥0.5 V/n S and <1.0 V/nS.
(21) For CLK & CLK slew rate ≥1.0 V/n S (single--ended).
(22) These parameters guarantee device timing, but they are not necessarily tested on each device. They may be
guaranteed by device design or tester correlation.
(23) Slew Rate is measured between V OH (ac) and V OL (ac).
Publication Release Date: Jan. 14, 2014
- 29 -
Revision: A04
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